The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 22, 2014
Filed:
Feb. 20, 2013
Qualcomm Incorporated, San Diego, CA (US);
Emmanouil Terrovitis, Foster City, CA (US);
QUALCOMM Incorporated, San Diego, CA (US);
Abstract
A clock multiplier circuit includes a clock generator, a delay element, a logic gate, and a duty cycle correction circuit. The clock generator generates a clock signal. The delay element generates a delayed clock signal in response to the clock signal. The logic gate generates a frequency-multiplied clock signal in response to the clock signal and the delayed clock signal. The duty cycle correction circuit generates an adjustment signal based at least in part on the frequency-multiplied clock signal. The clock generator adjusts a duty cycle of the clock signal in response to the adjustment signal.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile