The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 22, 2014

Filed:

Apr. 15, 2011
Applicant:

Yoshitaka Sugawara, Hitachi, JP;

Inventor:

Yoshitaka Sugawara, Hitachi, JP;

Assignees:

Yoshitaka Sugawara, Hitachi-shi, JP;

Fuji Electric Co., Ltd., Kawasaki-shi, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/80 (2006.01); H01L 21/70 (2006.01); H01L 29/66 (2006.01); H01L 23/62 (2006.01); H01L 27/06 (2006.01); H01L 29/02 (2006.01); H01L 27/02 (2006.01); H01L 29/739 (2006.01); H01L 29/06 (2006.01); H01L 29/16 (2006.01); H01L 29/45 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0657 (2013.01); H01L 29/0615 (2013.01); H01L 29/0696 (2013.01); H01L 29/739 (2013.01); H01L 29/0638 (2013.01); H01L 29/7397 (2013.01); H01L 29/1608 (2013.01); H01L 29/45 (2013.01); H01L 29/0661 (2013.01);
Abstract

A combined switching device includes a MOSFET disposed in a MOSFET area and IGBTs disposed in IGBT areas of a SiC substrate. The MOSFET and the IGBTs have gate electrodes respectively connected, a source electrode and emitter electrodes respectively connected, and a drain electrode and a collector electrode respectively connected. The MOSFET and the IGBTs are disposed with a common n-buffer layer. A top surface element structure of the MOSFET and top surface element structures of the IGBTs are disposed on the first principal surface side of the SiC substrate. Concave portions and convex portions are disposed on the second principal surface side of the SiC substrate. The MOSFET is disposed at a position corresponding to the convex portion of the SiC substrate. The IGBTs are disposed at positions corresponding to the concave portions of the SiC substrate.


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