The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 22, 2014
Filed:
Dec. 07, 2012
Contour Semiconductor, Inc., North Billerica, MA (US);
Daniel R. Shepard, North Hampton, NH (US);
Mac D. Apodaca, San Jose, CA (US);
Thomas Michael Trent, Nashua, NH (US);
James Juen Hsu, Saratoga, CA (US);
Contour Semiconductor, Inc., North Billerica, MA (US);
Abstract
The present invention is a method of incorporating a non-volatile memory into a CMOS process that requires four or fewer masks and limited additional processing steps. The present invention is an epi-silicon or poly-silicon process sequence that is introduced into a standard CMOS process (i) after the MOS transistors' gate oxide is formed and the gate poly-silicon is deposited (thereby protecting the delicate surface areas of the MOS transistors) and (ii) before the salicided contacts to those MOS transistors are formed (thereby performing any newly introduced steps having an elevated temperature, such as any epi-silicon or poly-silicon deposition for the formation of diodes, prior to the formation of that salicide). A 4Fmemory array is achieved with a diode matrix wherein the diodes are formed in the vertical orientation.