The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 22, 2014

Filed:

Aug. 06, 2012
Applicants:

Byung Du Ahn, Hwaseong-si, KR;

Jun Hyung Lim, Seoul, KR;

Jin Seong Park, Cheonan-si, KR;

Inventors:

Byung Du Ahn, Hwaseong-si, KR;

Jun Hyung Lim, Seoul, KR;

Jin Seong Park, Cheonan-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/16 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02565 (2013.01); H01L 21/02656 (2013.01);
Abstract

A method for manufacturing a thin film transistor array panel according to an exemplary embodiment of the present invention includes, forming a gate electrode, a gate insulating layer, and an oxide semiconductor layer on a substrate, first heat treating the substrate comprising the oxide semiconductor layer, forming a source electrode and a drain electrode on the oxide semiconductor layer, the source and drain electrodes facing each other, and forming a passivation layer on the source electrode and the drain electrode. The first heat treating is performed at more than 1 atmosphere and at most 50 or less atmospheres.


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