The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 15, 2014
Filed:
Jan. 02, 2013
International Business Machines Corporation, Armonk, NY (US);
Manikandan Viswanath, South Burlington, VT (US);
Samuel I. Ward, Austin, TX (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A netlist for an integrated circuit design is constrained by virtual or 'soft' pins to control or stabilize the placement of logic such as an architectural logic path. One soft pin is inserted at a fixed location proximate an input net of the path and is interconnected with the input net, and another is inserted at a fixed location proximate the output net and is interconnected with the output net. Cell placement is then optimized while maintaining the virtual pins at their fixed locations. More than two virtual pins may be inserted to bound a cluster of logic. The virtual pins may lie along the input/output nets. Pseudo-net weights are assigned to pseudo-nets formed between a cell and the virtual pins, and the pseudo-net weight can be increased for each placement iteration.