The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 15, 2014

Filed:

Jul. 27, 2009
Applicants:

Reza M. Bacchus, Spring, TX (US);

Vincent Nguyen, Houston, TX (US);

Melvin K. Benedict, Magnolia, TX (US);

Inventors:

Reza M. Bacchus, Spring, TX (US);

Vincent Nguyen, Houston, TX (US);

Melvin K. Benedict, Magnolia, TX (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/00 (2006.01); G06F 1/26 (2006.01); G06F 1/32 (2006.01); G11C 5/14 (2006.01); G11C 5/04 (2006.01);
U.S. Cl.
CPC ...
G11C 5/04 (2013.01); G06F 1/3225 (2013.01); G11C 5/147 (2013.01);
Abstract

Embodiments of the present invention are directed to a memory subsystem comprising a memory controller, multiple memory modules interconnected with the memory controller by one or more communications media, each memory module comprising a substrate to which multiple memory chips are mounted and electronically connected to the communications media, and a power-supply signal routed to two or more voltage regulators within the memory subsystem from a system power supply, the voltage regulators outputting two or more internal power signals, each power signal providing a different, regulated voltage, which are routed to each of the memory chips. Another embodiment of the present invention is directed to a memory module comprising a substrate to which multiple memory chips are mounted and two or more voltage regulators mounted to, or fabricated within, the substrate.


Find Patent Forward Citations

Bacchus, Reza. (2014). Method and system for power-efficient and non-signal-degrading voltage regulation in memory subsystems (U.S. Patent No. 8782452). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8782452

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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