The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 15, 2014
Filed:
Aug. 27, 2010
Applicants:
Haojen Cheng, Santa Clara, CA (US);
Feng-yu Lee, Hsinchu, TW;
Qinfang Sun, Cupertino, CA (US);
Inventors:
Assignee:
QUALCOMM Incorporated, San Diego, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04B 1/00 (2006.01);
U.S. Cl.
CPC ...
Abstract
A hybrid bit detection circuit for receiving bits from different global positioning systems, e.g. GPS and GLONASS, can include a frequency lock loop (FLL) for receiving the global positioning bits and removing Doppler frequency error and an integrate and dump (I&D) block coupled to an output of the FLL. A coherent detection circuit can be coupled to an output of the FLL and an output of the integrated and dump block. A differential detection circuit can be coupled to an output of the I&D block. Two parity check blocks can be coupled to outputs of the coherent and differential detection circuits.