The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 15, 2014
Filed:
Jun. 28, 2012
Chihhung Liao, Fremont, CA (US);
Phu Nguyen, Dublin, CA (US);
Vimal R. Patel, Rochester, MN (US);
George F. Paulik, Rochester, MN (US);
Peder J. Paulson, Rochester, MN (US);
Brian J. Reed, Rochester, MN (US);
Salvatore N. Storino, Rochester, MN (US);
Chihhung Liao, Fremont, CA (US);
Phu Nguyen, Dublin, CA (US);
Vimal R. Patel, Rochester, MN (US);
George F. Paulik, Rochester, MN (US);
Peder J. Paulson, Rochester, MN (US);
Brian J. Reed, Rochester, MN (US);
Salvatore N. Storino, Rochester, MN (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
An eFuse circuit may include a wordline, a first eFuse, a first logic gate, a first blowFET, and a first bitline discharge device. The first eFuse may have a first end coupled to the wordline and a second end. The first eFuse may have a first resistance when unblown and a second resistance when blown. The first logic gate may be coupled to the first end of the first eFuse. The first logic gate may be capable of driving enough current to blow the first eFuse. The first blowFET may have a source coupled to a first supply voltage, a gate coupled to a program signal, and a drain coupled to the second end of the first eFuse. The first bitline discharge device may have a gate coupled to the second end of the first eFuse, a source coupled to the first supply voltage, and a drain coupled to a first bitline.