The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 15, 2014

Filed:

Mar. 19, 2012
Applicants:

Jinho DO, Gyeonggi-do, KR;

Hajin Lim, Seoul, KR;

Weonhong Kim, Gyeonggi-do, KR;

Kyungil Hong, Gyeonggi-do, KR;

Moonkyun Song, Gyeonggi-do, KR;

Inventors:

Jinho Do, Gyeonggi-do, KR;

Hajin Lim, Seoul, KR;

WeonHong Kim, Gyeonggi-do, KR;

Kyungil Hong, Gyeonggi-do, KR;

Moonkyun Song, Gyeonggi-do, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 21/265 (2006.01); H01L 29/10 (2006.01); H01L 29/165 (2006.01); H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
H01L 29/165 (2013.01); H01L 29/66575 (2013.01); H01L 29/7848 (2013.01); H01L 21/26506 (2013.01); H01L 21/823807 (2013.01); H01L 29/78 (2013.01); H01L 29/1054 (2013.01); H01L 21/823814 (2013.01); H01L 29/66636 (2013.01); H01L 21/2822 (2013.01); H01L 21/28185 (2013.01);
Abstract

A substrate including an NMOS transistor region and a PMOS transistor region is prepared. A silicon-germanium layer is formed on the PMOS transistor region. Nitrogen atoms are injected in an upper portion of the silicon-germanium layer. A first gate dielectric layer is formed on the NMOS transistor region and the PMOS transistor region. The nitrogen atoms are injected into the upper portion of the silicon-germanium layer before forming the first gate dielectric layer.


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