The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 08, 2014
Filed:
Jan. 14, 2011
Frank Borkam, San Carlos, CA (US);
Hemlata Gupta, Hopewell Jct., NY (US);
David J. Hathaway, Underhill, VT (US);
Kerim Kalafala, Rhinebeck, NY (US);
Vasant Rao, Fishkill, NY (US);
Alex Rubin, San Jose, CA (US);
Frank Borkam, San Carlos, CA (US);
Hemlata Gupta, Hopewell Jct., NY (US);
David J. Hathaway, Underhill, VT (US);
Kerim Kalafala, Rhinebeck, NY (US);
Vasant Rao, Fishkill, NY (US);
Alex Rubin, San Jose, CA (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Determining static timing analysis margin on non-controlling inputs of clock shaping and other digital circuits using reverse merge timing includes: selecting one or more circuits within the logic design having a plurality of inputs and using reverse merge; identifying a controlling input of the selected circuit from among this plurality of inputs; and determining for at least one non-controlling input of the circuit, a timing value that may be used to drive design optimization based on the difference between arrival times of the controlling and non-controlling inputs.