The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 08, 2014

Filed:

Jan. 17, 2012
Applicants:

Pavel A. Panteleev, Moscow, RU;

Elyar E. Gasanov, Moscow, RU;

Ilya V. Neznanov, Moscow, RU;

Andrey P. Sokolov, Moscow, RU;

Yurii S. Shutkin, Moscow, RU;

Inventors:

Pavel A. Panteleev, Moscow, RU;

Elyar E. Gasanov, Moscow, RU;

Ilya V. Neznanov, Moscow, RU;

Andrey P. Sokolov, Moscow, RU;

Yurii S. Shutkin, Moscow, RU;

Assignee:

LSI Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 13/00 (2006.01); G11C 29/00 (2006.01); H03M 13/15 (2006.01); H03M 13/35 (2006.01); H03M 13/37 (2006.01); H03M 7/40 (2006.01); H04L 1/00 (2006.01);
U.S. Cl.
CPC ...
H03M 13/1515 (2013.01); H03M 13/152 (2013.01); H03M 13/6516 (2013.01); H03M 13/617 (2013.01); H03M 13/611 (2013.01); H03M 13/15 (2013.01); H03M 13/35 (2013.01); H03M 13/3707 (2013.01); H03M 13/6318 (2013.01); H03M 7/40 (2013.01); H03M 7/4031 (2013.01); H03M 7/4093 (2013.01); H04L 1/0047 (2013.01);
Abstract

An apparatus generally having a plurality of first circuits and a second circuit is disclosed. The first circuits may be configured to (i) generate a plurality of intermediate bits by dividing a plurality data bits by a plurality of minimal polynomials of an encoding along a first path and (ii) generate a plurality of parity bits by multiplying the intermediate bits by the minimal polynomials along a second path. A number of the parity bits may be variable based on a configuration signal. The second circuit may be configured to (i) delay the data bits and (ii) generate a plurality of code bits by appending the parity bits to a last of the data bits.


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