The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 08, 2014
Filed:
Mar. 25, 2011
Gregory Mchale, Brookline, NH (US);
Brian G. Nadeau, Nashua, NH (US);
Bryan K. Panner, Windham, NH (US);
Peter J. Hunter, Amherst, NH (US);
Damon Hung, Providence, RI (US);
Janice Lacy, Temple, NH (US);
Gregory McHale, Brookline, NH (US);
Brian G. Nadeau, Nashua, NH (US);
Bryan K. Panner, Windham, NH (US);
Peter J. Hunter, Amherst, NH (US);
Damon Hung, Providence, RI (US);
Janice Lacy, Temple, NH (US);
Dell Products, L.P., Round Rock, TX (US);
Abstract
A hybrid storage array one using two or more storage device tiers. In one implementation, two tiers may be provided by solid state drives (SSDs) and hard disk drives (HDDs). Host application access patterns of a certain type determined to be relatively slow, such as random writes, are detected. The random writes are collected and written to a special reserve space, such as a portion of the SSD storage tier, referred to as a write cache extension. The write cache extension absorbs such accesses that would otherwise be written to HDD storage directly. Data structures are created in a cache memory local to an array controller representing the location on SSD reserve space to which the writes were committed and a location in the storage system where they were originally intended to go. The write cache extension can be enabled all of the time, or only when the array controller write cache experiences certain operating conditions, such as when its utilization exceeds a certain predetermined amount. The approach improves the overall performance of the hybrid array.