The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 08, 2014

Filed:

Jun. 10, 2011
Applicants:

John F. Bulzacchelli, Yonkers, NY (US);

Timothy O. Dickson, Danbury, CT (US);

Daniel J. Friedman, Sleepy Hollow, NY (US);

Yong Liu, Rye, NY (US);

Sergey V. Rylov, White Plains, NY (US);

Inventors:

John F. Bulzacchelli, Yonkers, NY (US);

Timothy O. Dickson, Danbury, CT (US);

Daniel J. Friedman, Sleepy Hollow, NY (US);

Yong Liu, Rye, NY (US);

Sergey V. Rylov, White Plains, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04J 3/06 (2006.01);
U.S. Cl.
CPC ...
Abstract

Methods and apparatus are provided for timing recovery for an input/output bus with link redundancy. A parallel input/output interface receiver includes a plurality of data receivers, each configured to respectively receive input data from a respective one of n+m channels, where n is an integer greater than one and m is an integer greater than or equal to one. The input data is non-calibration data for the n channels and is calibration data for the m channels. The interface receiver further includes a first phase adjustor configured to provide a first clock signal to the plurality of data receivers for sampling of only the non-calibration data at any given time, and a second phase adjustor configured to provide a second clock signal to the plurality of data receivers for sampling of only the calibration data at any given time.


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