The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 08, 2014
Filed:
Dec. 09, 2011
Keith R. Schakel, San Jose, CA (US);
Suresh Natarajan Rajan, San Jose, CA (US);
Michael John Sebastian Smith, Palo Alto, CA (US);
David T. Wang, Thousand Oaks, CA (US);
Frederick Daniel Weber, San Jose, CA (US);
Keith R. Schakel, San Jose, CA (US);
Suresh Natarajan Rajan, San Jose, CA (US);
Michael John Sebastian Smith, Palo Alto, CA (US);
David T. Wang, Thousand Oaks, CA (US);
Frederick Daniel Weber, San Jose, CA (US);
Google Inc., Mountain View, CA (US);
Abstract
An apparatus includes multiple first memory circuits, in which the multiple first memory circuits are positioned on at least one dual in-line memory module (DIMM). The apparatus includes an interface circuit operable to interface the first memory circuits with a system; present the first memory circuits to the system as one or more simulated second memory circuits; transmit, in response to receiving a first refresh control signal sent from the system to the one or more simulated memory circuits, multiple second refresh control signals to the first memory circuits; and apply a respective delay to each second refresh control signal transmitted to a corresponding first memory circuit. Each simulated second memory circuit has a corresponding second memory capacity that is greater than a first memory capacity of at least one of the first memory circuits.