The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 08, 2014

Filed:

Apr. 04, 2007
Applicants:

William J. Donahue, Pepperell, MA (US);

Oh-hun Kwon, Westborough, MA (US);

F. Michael Mahoney, Holliston, MA (US);

John D. Pietras, Sutton, MA (US);

Inventors:

William J. Donahue, Pepperell, MA (US);

Oh-Hun Kwon, Westborough, MA (US);

F. Michael Mahoney, Holliston, MA (US);

John D. Pietras, Sutton, MA (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01M 8/00 (2006.01); H01M 8/10 (2006.01); H01M 8/24 (2006.01); H01M 2/08 (2006.01); H01M 2/14 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present disclosure is directed to an integrated SOFC stack including, a first cell having a cathode layer, an electrolyte layer overlying the cathode layer, and an anode layer overlying the electrolyte layer. The SOFC stack also includes a second cell having a cathode layer, an electrolyte layer overlying the cathode layer, and an anode overlying the electrolyte layer. The SOFC stack further includes a ceramic interconnect layer between the first cell and the second cell, the ceramic interconnect layer having a first high temperature bonding region along the interfacial region between the first cell and the ceramic interconnect layer. The ceramic interconnect layer also includes a second high temperature bonding region along the interfacial region between the second cell and the ceramic interconnect layer.


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