The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 01, 2014
Filed:
Jun. 22, 2012
Mark E. Wentroble, Plano, TX (US);
T-pinn R. Koh, Allen, TX (US);
Mark E. Wentroble, Plano, TX (US);
T-Pinn R. Koh, Allen, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
An apparatus is provided. Physical medium dependent (PMD) sublayer logic is configured to communicate with a communications medium. Physical medium attachment (PMA) sublayer logic is coupled to the PMD logic. Forward error correction (FEC) sublayer logic is coupled to the PMA sublayer logic, and physical coding (PCS) sublayer logic is configured to communicate with an interface. A transmit path is coupled to the transmit data in a second clock domain to the FEC sublayer logic. A first read pointer circuit is coupled to transmit path. A write pointer circuit is coupled to the transmit path. A receive path is coupled to receive data in the second clock domain from the FEC sublayer logic. A second read pointer circuit is coupled to the receive path, where the first read pointer circuit, the second read pointer circuit, and the write pointer circuits are each configured to detect gaps between the first and second clock domains.