The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 01, 2014
Filed:
Jan. 18, 2012
Wayne L. Moul, Loveland, CO (US);
Robert J. Behnke, Ii, Erie, CO (US);
Scott E. M. Frushour, Boulder, CO (US);
Jeffrey L. Jensen, Boulder, CO (US);
Wayne L. Moul, Loveland, CO (US);
Robert J. Behnke, II, Erie, CO (US);
Scott E. M. Frushour, Boulder, CO (US);
Jeffrey L. Jensen, Boulder, CO (US);
Covidien LP, Mansfield, MA (US);
Abstract
A multi-layer printed circuit board includes a first layer stack and a second layer stack coupled to the first layer stack. The first layer stack includes a first electrically-insulating layer, a second electrically-insulating layer, and a first electrically-conductive layer disposed between the first and second electrically-insulating layers. The second layer includes a third electrically-insulating layer and a second electrically-conductive layer. The first layer stack and/or the second layer stack include a cut-out area defining a void that extends therethrough. The multi-layer printed circuit board further includes a first signal layer disposed in association with the first electrically-insulating layer of the first layer stack or the third electrically-insulating layer of the second layer stack, a second signal layer disposed in association with the second electrically-insulating layer of the first layer stack, and a device at least partially disposed within the cut-out area and electrically-coupled to the first and second signal layers.