The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 01, 2014

Filed:

Sep. 28, 2012
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Solomon Assefa, Ossining, NY (US);

Tymon Barwicz, Yorktown Heights, NY (US);

Swetha Kamlapurkar, Ossining, NY (US);

Marwan H. Khater, Astoria, NY (US);

Steven M. Shank, Essex Junction, NY (US);

Yurii A. Vlasov, Katonah, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of forming an integrated photonic semiconductor structure having a photonic device and a CMOS device may include depositing a first silicon nitride layer having a first stress property over the photonic device, depositing an oxide layer having a stress property over the deposited first silicon nitride layer, and depositing a second silicon nitride layer having a second stress property over the oxide layer. The deposited first silicon nitride layer, the oxide layer, and the second silicon nitride layer encapsulate the photonic device.


Find Patent Forward Citations

Assefa, Solomon. (2014). Stress engineered multi-layers for integration of cmos and si nanophotonics (U.S. Patent No. 8765536). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8765536

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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