The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 01, 2014

Filed:

Mar. 14, 2013
Applicant:

Dongbu Hitek Co., Ltd., Gyeonggi-do, KR;

Inventors:

Chung Kyung Jung, Gyeonggi-do, KR;

Sung Wook Joo, Gyeongsangnam-do, KR;

Assignee:

Dongbu HiTek Co., Ltd., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/44 (2006.01); H01L 21/4763 (2006.01); H01L 21/302 (2006.01); H01L 21/461 (2006.01); H01L 21/768 (2006.01); B81B 7/00 (2006.01); H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 21/52 (2006.01); H01L 29/40 (2006.01); G01P 15/00 (2006.01); G01P 15/135 (2006.01); H01H 35/02 (2006.01); H01H 35/14 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76843 (2013.01); B81B 7/00 (2013.01); H01L 23/49816 (2013.01);
Abstract

A method for manufacturing a semiconductor device including at least one of the following steps: (1) Forming a lower electrode pattern on/over a substrate. (2) Forming a first interlayer insulating layer on the lower electrode pattern. (3) Forming an upper electrode pattern on the first interlayer insulating layer. (4) Forming a passivation layer on a side of the upper electrode pattern. (5) Forming a second interlayer insulating layer on the upper electrode pattern. (6) Etching the second interlayer insulating layer to form a cavity which exposes the passivation layer. (7) Forming a contact ball in the cavity.


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