The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 01, 2014
Filed:
Mar. 24, 2010
Applicants:
Toshiaki Ono, Tokyo, JP;
Takayuki Kihara, Tokyo, JP;
Yumi Hoshino, Tokyo, JP;
Inventors:
Assignee:
Sumco Corporation, Tokyo, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/66 (2006.01); H01L 21/302 (2006.01); H01L 29/36 (2006.01); H01L 21/324 (2006.01); C30B 29/06 (2006.01); C30B 33/02 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
C30B 33/02 (2013.01); H01L 29/36 (2013.01); H01L 29/7833 (2013.01); H01L 21/324 (2013.01); C30B 29/06 (2013.01);
Abstract
This method of manufacturing a silicon wafer has a step of preparing a wafer, in which a surface of the silicon wafer is surface-treated, a step of setting stress, in which the stress S (MPa) subjected on the wafer is set, a step of inspecting, in which a defect on a surface of the wafer is inspected, and a step of determining, in which the wafer is evaluated if the wafer satisfies a criterion. In this method, it is possible to manufacture a wafer with cracking resistance even if it is subjected to a millisecond annealing by the FLA annealing treatment.