The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 24, 2014
Filed:
Sep. 17, 2010
Balaji Prabhakar, Tamilnadu, IN;
Sunil Kumar Singla, Ludhiana, IN;
Balaji Prabhakar, Tamilnadu, IN;
Sunil Kumar Singla, Ludhiana, IN;
Applied Micro Circuits Corporation, Sunnyvale, CA (US);
Abstract
A circuit analysis tool is provided for die size reduction analysis. A processor determines a first initial output slack time. If the first initial output slack time is greater than zero, a first circuit element is modeled with a second die area, less than the first die area. The second die area is associated with a third delay greater than the first delay. Then, the second data signal is modeled equal to the first data signal with the third delay. If a first modified output slack time is greater than or equal to zero, the first circuit element first die can be replaced with the second die. If the first modified output slack time is a first value less than zero, a first delay is added to the clock signal that is greater than or equal to the first value.