The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 24, 2014

Filed:

Aug. 30, 2012
Applicants:

Toshihiko Funaki, Kanagawa, JP;

Toshiharu Okamoto, Kanagawa, JP;

Muneaki Matsushige, Kanagawa, JP;

Kenichi Kuboyama, Kanagawa, JP;

Shuuichi Senou, Kanagawa, JP;

Susumu Takano, Kanagawa, JP;

Inventors:

Toshihiko Funaki, Kanagawa, JP;

Toshiharu Okamoto, Kanagawa, JP;

Muneaki Matsushige, Kanagawa, JP;

Kenichi Kuboyama, Kanagawa, JP;

Shuuichi Senou, Kanagawa, JP;

Susumu Takano, Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 7/10 (2006.01); G11C 8/00 (2006.01); G11C 8/06 (2006.01); G11C 8/12 (2006.01); G11C 11/4096 (2006.01);
U.S. Cl.
CPC ...
G11C 7/1048 (2013.01); G11C 11/4096 (2013.01); G11C 7/10 (2013.01); G11C 7/1006 (2013.01); G11C 7/00 (2013.01); G11C 8/12 (2013.01);
Abstract

A semiconductor apparatus according to an aspect of the present invention includes first and second bus-interface circuits, a first memory core connected to the first bus-interface circuit through a first data bus, the first memory core being connected to a first access control signal output from the first bus-interface circuit, a second memory core connected to the second bus-interface circuit through a second data bus, and a select circuit that selectively connects one of the first access control signal and a second access control signal output from the second bus-interface circuit to the second memory core.


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