The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 24, 2014

Filed:

Jun. 30, 2011
Applicants:

Tae-young Choi, Seoul, KR;

BO Sung Kim, Seoul, KR;

Young Min Kim, Yongin-si, KR;

Seon-pil Jang, Seoul, KR;

Kang Moon JO, Seoul, KR;

Yeon Taek Jeong, Seoul, KR;

Ki Beom Lee, Seoul, KR;

Inventors:

Tae-Young Choi, Seoul, KR;

Bo Sung Kim, Seoul, KR;

Young Min Kim, Yongin-si, KR;

Seon-Pil Jang, Seoul, KR;

Kang Moon Jo, Seoul, KR;

Yeon Taek Jeong, Seoul, KR;

Ki Beom Lee, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02F 1/136 (2006.01);
U.S. Cl.
CPC ...
Abstract

A thin film transistor array panel includes a source electrode and a drain electrode on an insulating substrate, an oxide semiconductor on the insulating substrate and overlapping the source electrode and the drain electrode, a passivation layer overlapping the oxide semiconductor and on the insulating substrate, a gate electrode on the passivation layer, and a pixel electrode connected to the drain electrode. The gate electrode and the pixel electrode include a same material. The oxide semiconductor is between the source electrode and the gate electrode, and between the drain electrode and the gate electrode in a cross-sectional view of the thin film transistor array panel.


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