The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 17, 2014
Filed:
Mar. 20, 2013
Renesas Electronics Corporation, Kanagawa, JP;
Keiichi Suzuki, Kanagawa, JP;
Renesas Electronics Corporation, Kanagawa, JP;
Abstract
In an LSI designing support device and method, in which in an LSI circuit is designed including a logic gate and an FET, a possibility that a steady-state flow-through current from a power source to a ground is generated is determined. In an inputted netlist including a logic gate and an FET, extraction is made of a flow-through condition function which expresses, in terms of a Boolean expression, on/off of an FET arranged in a path from a power source to a ground or a path from the output of a logic gate to the power source or to the ground. A flow-through condition determining Boolean expression of a logic circuit which supplies an input to the flow-through condition function is extracted. The Boolean expression is degenerated with logic equivalence maintained, and the existence or nonexistence of a possibility of satisfying a flow-through condition is determined.