The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 17, 2014

Filed:

Dec. 16, 2010
Applicants:

Samuel D. Naffziger, Fort Collins, CO (US);

John P. Petry, San Diego, CA (US);

Kiran Bondalapati, Los Altos, CA (US);

William A. Hughes, San Jose, CA (US);

Inventors:

Samuel D. Naffziger, Fort Collins, CO (US);

John P. Petry, San Diego, CA (US);

Kiran Bondalapati, Los Altos, CA (US);

William A. Hughes, San Jose, CA (US);

Assignee:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A processor power limiter and method is provided. The processor includes a first programmable location configured to store a processor power target. A power monitor is configured to estimate a power dissipation due to processor load. A power controller is configured to adjust a processor power parameter based on the power target and the power dissipation. The processor may include an interface for an operating system. A second programmable location may be configured to store a software processor power target accessible by the operating system. The processor may also include a sideband interface for an external agent. A third programmable location may be configured to store an agent processor power target accessible by the external agent. The power controller may be configured to adjust a processor core voltage and/or frequency such that the power dissipation stays below the processor power target, software processor power target and the agent processor power target.


Find Patent Forward Citations

Naffziger, Samuel. (2014). System for processor power limit management (U.S. Patent No. 8756442). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8756442

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…