The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 17, 2014
Filed:
Feb. 04, 2014
Applicant:
Sypris Electronics Llc, Tampa, FL (US);
Inventor:
Douglas J. Gardner, Tampa, FL (US);
Assignee:
Sypris Electronics, LLC, Tampa, FL (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 21/00 (2013.01); G06F 21/10 (2013.01); G06F 21/60 (2013.01); G06F 21/74 (2013.01); G06F 21/62 (2013.01); G06F 21/53 (2013.01); G06F 21/57 (2013.01);
U.S. Cl.
CPC ...
G06F 21/57 (2013.01); G06F 21/10 (2013.01); G06F 21/606 (2013.01); G06F 21/74 (2013.01); G06F 21/6218 (2013.01); G06F 21/53 (2013.01); G06F 2221/2105 (2013.01);
Abstract
A multi-mode Trusted Computing Platform (TCP) comprising a Field Programmable Gate Array (FPGA) device that includes a Type-1-compliant root of trust (ROT), a memory containing a Type-1 security boot image and at least one lower-security boot image, and a memory containing a Type-1-associated operating system (OS) image and at least one lower-security-associated OS image. The TCP is configured to execute a multi-stage boot process that, depending on the presence of one or more valid external inputs, selects and initiates either a Type-1 TCP computing mode or a lower-assurance computing mode.