The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 17, 2014

Filed:

Jul. 27, 2007
Applicants:

Michiaki Matsuo, San Jose, CA (US);

Hideki Aoyagi, Miyagi, JP;

Hitoshi Asano, Miyagi, JP;

Kazuya Toki, Miyagi, JP;

Inventors:

Michiaki Matsuo, San Jose, CA (US);

Hideki Aoyagi, Miyagi, JP;

Hitoshi Asano, Miyagi, JP;

Kazuya Toki, Miyagi, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 27/06 (2006.01);
U.S. Cl.
CPC ...
Abstract

A received pulse signal based on an on-off keying modulation scheme is alternately sampled by AD conversion sections operated by a clock signal whose frequency is one-half of a transmission rate. In the synchronization, amounts of delay in sampling timing adjustment sections are made different from each other, whereby phases of two different points in a symbol pulse are sampled. An amount of delay in a variable delay section is adjusted in accordance with a result of comparison of the sampled values, thereby achieving synchronization. At the time of demodulation, the amount of delay in the variable delay section is held, and the amounts of delay in the sampling timing adjustment sections are switched to the same value, and the symbol pulse is alternately sampled. The sampled values are subjected to threshold value determination, and the determination result is subjected to parallel-to-serial conversion, whereby a demodulation output is acquired.


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