The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 17, 2014

Filed:

Apr. 06, 2012
Applicants:

Ambica Ashok, Austin, TX (US);

Ravindraraj Ramaraju, Round Rock, TX (US);

Andrew C. Russell, Austin, TX (US);

Inventors:

Ambica Ashok, Austin, TX (US);

Ravindraraj Ramaraju, Round Rock, TX (US);

Andrew C. Russell, Austin, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 8/00 (2006.01); G11C 11/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A multi-port memory cell of a multi-port memory array includes a first inverter that inverter is disabled by a first subset of write word lines and a second inverter, cross coupled with the first inverter, wherein the second inverter is disabled by a second subset of the plurality of write word lines. A first selection circuit has data inputs coupled to a first subset of a plurality of write bit lines, selection inputs coupled to the first subset of the plurality of write word lines, and an output coupled to the input of the second inverter. The second selection circuit has data inputs coupled to a second subset of the plurality of write bit lines, selection inputs coupled to the second subset of the plurality of write word lines, and an output coupled to the input of the first inverter.


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