The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 17, 2014

Filed:

Nov. 17, 2011
Applicants:

Lakshmikantha V. Holla, Karnataka, IN;

Vinod J. Menezes, Karnataka, IN;

Theodore W. Houston, Richardson, TX (US);

Michael Patrick Clinton, Allen, TX (US);

Inventors:

Lakshmikantha V. Holla, Karnataka, IN;

Vinod J. Menezes, Karnataka, IN;

Theodore W. Houston, Richardson, TX (US);

Michael Patrick Clinton, Allen, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/08 (2006.01); G11C 11/417 (2006.01); G11C 11/413 (2006.01);
U.S. Cl.
CPC ...
G11C 8/08 (2013.01); G11C 11/413 (2013.01); G11C 11/417 (2013.01);
Abstract

A memory circuit includes a bit cell that receives a word line, complementary bit lines and an array supply voltage; a word line driver coupled to the word line, the word line driver receiving one of the array supply voltage and a periphery supply voltage; and a word line suppression circuit coupled to the word line. The word line suppression circuit includes a diode and a switch coupled in series. The switch is responsive to the array supply voltage. The word line suppression circuit limits a word line voltage to a value lower than the array supply voltage such that the static noise margin (SNM) of the bit cell is increased.


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