The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 17, 2014

Filed:

Jul. 25, 2012
Applicants:

Wei LI, Fremont, CA (US);

Weiqi Ding, Fremont, CA (US);

Wilson Wong, San Francisco, CA (US);

Inventors:

Wei Li, Fremont, CA (US);

Weiqi Ding, Fremont, CA (US);

Wilson Wong, San Francisco, CA (US);

Assignee:

Altera Corporation, San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/10 (2006.01);
U.S. Cl.
CPC ...
Abstract

An integrated circuit with a pipeline analog-to-digital (A/D) converter and associated calibration circuitry is provided. The A/D converter may include multiple series-connected pipeline stages at least some of which are implemented using a switched capacitor configuration. The calibration circuitry may include an analog error correction circuit, a digital error correction circuit, and a calibration control circuit for coordinating the operation of the analog and digital error correction circuits. During calibration operations, the analog error correction circuit may be used to suitably adjust a gain setting for each pipeline stage, whereas the digital error correction circuit may be used to compute a code offset value for each pipeline stage. Calibration may proceed from a least-significant-bit pipeline stage towards a most-significant-bit pipeline stage, one stage at a time.


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