The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 17, 2014
Filed:
Nov. 23, 2010
Toshiya Uozumi, Tokyo, JP;
Keisuke Ueda, Tokyo, JP;
Mitsunori Samata, Tokyo, JP;
Satoru Yamamoto, Tokyo, JP;
Russell P Mohn, Tarrytown, NY (US);
Aleksander Dec, Tarrytown, NY (US);
Ken Suyama, Tarrytown, NY (US);
Toshiya Uozumi, Tokyo, JP;
Keisuke Ueda, Tokyo, JP;
Mitsunori Samata, Tokyo, JP;
Satoru Yamamoto, Tokyo, JP;
Russell P Mohn, Tarrytown, NY (US);
Aleksander Dec, Tarrytown, NY (US);
Ken Suyama, Tarrytown, NY (US);
Renesas Electronics Corporation, Kanagawa, JP;
Epoch Microelectronics, Inc., Tarrytown, NY (US);
Abstract
In an ADPLL composed of a digital circuit, a technique improving phase difference detection in a vicinity of a phase difference of 0 (zero) is provided. A feedback loop comprises a PFD comparing phases and frequencies of a reference signal and a feedback signal, a TDC converting an output of the PFD into a digital value, a DLF removing a high frequency noise component from an output of the TDC, a DCO controlled based on an output of the DLF and a DIV frequency-dividing an output the DCO and outputting the feedback signal. An offset value is added at any portion of the feedback loop, a phase of the feedback signal is controlled and a value other than 0 is inputted to the TDC even when the ADPLL is locked.