The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 17, 2014

Filed:

Dec. 12, 2012
Applicant:

SK Hynix Inc., Icheon-si, KR;

Inventors:

Dae Han Kwon, Icheon-si, KR;

Yong Ju Kim, Icheon-si, KR;

Jae Min Jang, Icheon-si, KR;

Hae Rang Choi, Icheon-si, KR;

Assignee:

SK Hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/06 (2006.01);
U.S. Cl.
CPC ...
Abstract

A clock generation circuit includes a delay line, which delays an input clock and generates a delayed clock, a delay modeling unit, which delays the delayed clock by a modeled delay value and generates a feedback clock, a phase detection unit, which compares phases of the input clock and the feedback clock and generates a phase detection signal, a filter unit, which receives the phase detection signal and generates phase information, generates an update signal when a difference between the numbers of phase detection signals with a first and a second level generated is greater than or equal to a threshold value, and generates the update signal after a lapse of a predetermined time when the difference is less than the threshold value, and a delay line control unit, which sets a delay value of the delay line in response to the update signal and the phase information.


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