Pulse matching delay-locked loop

Abstract

A delay-locked loop (DLL) involves a pulse generating circuit that generates first and second pulses from an input clock signal. The second pulse is generated one clock signal period later than the first pulse. The first pulse is supplied to the input of a delay line. An edge of a delayed version of the first pulse as output from the delay line is phase-aligned with respect to a corresponding edge of the undelayed second pulse such that the DLL locks. The sending of pulses through the delay line of the DLL rather than clock signals having more edges per unit time helps reduce DLL aliasing problems and reduces the amount of switching in the delay line, thereby reducing power. consumption. A compact segmented delay line construction allows an input signal of arbitrary wave shape to be delayed by a fraction of the clock signal period.