The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8754667 B1

PDF
Full Text
Expired
Date of Patent:
Jun. 17, 2014

Filed:

Feb. 25, 2011
Applicants:

Chiaki Mimura, Yokohama, JP;

Kazuhiko Shimabayashi, Yokohama, JP;

Inventors:

Chiaki Mimura, Yokohama, JP;

Kazuhiko Shimabayashi, Yokohama, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/26 (2014.01);
U.S. Cl.
CPC ...
Abstract

A transition delay test is conducted such that an internal circuit that is a test object circuit in a semiconductor device is divided into a plurality of circuit blocks and a determination test is conducted while changing concurrently operating circuit blocks, a power supply noise generated during conduction of the determination test is detected, a suitable circuit scale on which the transition delay test can be normally conducted without being affected by the influence of the power supply noise is determined based on the result of the determination test and the detected power supply noise, and clocks to be supplied to the circuit blocks are controlled based on the determination result to limit the number of the concurrently operating circuit blocks.


Find Patent Forward Citations

Mimura, Chiaki. (2014). Semiconductor device test method and semiconductor device (U.S. Patent No. 8754667). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8754667

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