The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 17, 2014

Filed:

Apr. 26, 2013
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Hiroyuki Tomomatsu, Beppu, JP;

Motoaki Kusamaki, Beppu, JP;

Kohichi Kubota, Beppu, JP;

Yuta Masuda, Oita-Pref, JP;

Akihiro Sugihara, Beppu, JP;

Hiroshi Sera Kitada, Tokyo, JP;

Takeshi Konno, Ushiku, JP;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 31/0232 (2014.01); H01L 31/042 (2014.01); H01L 27/144 (2006.01); H01L 27/146 (2006.01); G11B 7/131 (2012.01); G11B 7/00 (2006.01);
U.S. Cl.
CPC ...
H01L 31/02327 (2013.01); H01L 31/042 (2013.01); H01L 27/1446 (2013.01); H01L 27/14643 (2013.01); G11B 7/131 (2013.01); G11B 2007/0006 (2013.01);
Abstract

A method of fabricating a photodiode array having different photodiode structures includes providing a semiconductor substrate having first and second diode areas including a bottom substrate portion doped with a first doping type, an intrinsic layer, and a top silicon layer doped with a second doping type. The second diode areas are implanted with the second doping type. A dopant concentration in the surface of the second diode areas is at least three times higher than in the first diode areas. The top silicon layer is thermally oxidized to form a thermal silicon oxide layer to provide a bottom Anti-Reflective Coating (ARC) layer. The second diode areas grow thermal silicon oxide thicker as compared to the first diode areas. A top ARC layer is deposited on the bottom ARC layer. First PDs are provided in the first diode areas and second PDs provided in the second diode areas.


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