The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 17, 2014

Filed:

Nov. 21, 2011
Applicants:

Dong-sik Lee, Yongin-si, KR;

Jang-hyun You, Seoul, KR;

Jee-hoon Han, Hwaseong-si, KR;

Young-woo Park, Seoul, KR;

Sung-hoi Hur, Seoul, KR;

Sang-ick Joo, Changwon-si, KR;

Inventors:

Dong-Sik Lee, Yongin-si, KR;

Jang-Hyun You, Seoul, KR;

Jee-Hoon Han, Hwaseong-si, KR;

Young-Woo Park, Seoul, KR;

Sung-Hoi Hur, Seoul, KR;

Sang-Ick Joo, Changwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/76 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of fabricating a nonvolatile memory device includes forming trenches in a substrate defining device isolation regions therein and active regions therebetween. The trenches and the active regions therebetween extend into first and second device regions of the substrate. A sacrificial layer is formed in the trenches between the active regions in the first device region, and an insulating layer is formed to substantially fill the trenches between the active regions in the second device region. At least a portion of the sacrificial layer in the trenches in the first device region is selectively removed to define gap regions extending along the trenches between the active regions in the first device region, while substantially maintaining the insulating layer in the trenches between the active regions in the second device region. Related methods and devices are also discussed.


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