The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 10, 2014

Filed:

Dec. 22, 2010
Applicants:

Jishan Ding, Shenzhen, CN;

Wei Huang, Shenzhen, CN;

Wei Lai, Shenzhen, CN;

Jianbing Wang, Shenzhen, CN;

Kedong Yu, Shenzhen, CN;

Zhiyong Liao, Shenzhen, CN;

Inventors:

Jishan Ding, Shenzhen, CN;

Wei Huang, Shenzhen, CN;

Wei Lai, Shenzhen, CN;

Jianbing Wang, Shenzhen, CN;

Kedong Yu, Shenzhen, CN;

Zhiyong Liao, Shenzhen, CN;

Assignee:

ZTE Corporation, Shenzhen, Guangdong Province, CN;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/12 (2006.01);
U.S. Cl.
CPC ...
Abstract

A Quad-Data Rate (QDR) controller and an implementation method thereof are disclosed in the present invention. The controller includes: an arbiter, a control state machine, a read data sampling clock generating module, a read data path module and a read data path calibrating module. The arbiter arbitrates commands and data according to the state of the control state machine; the read data sampling clock generating module generates read data sampling clocks with the same source and same frequency and different phases; the read data path calibrating module determines, among the generated read data sampling clocks, sampling clocks of positive edge data and negative edge data for the read data path module to read data by reading training words when the control state machine is in 'read data path calibrating state'; the read data path module synchronizes the positive edge read data and negative edge data in a non-system clock domain to the system clock domain according to the determined sampling clocks. The present invention has a shorter delay and does not need any programmable delay element, and is easy to implement.


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