The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 10, 2014
Filed:
Sep. 28, 2011
Brian Fahs, Los Altos, CA (US);
Henry Packard Moreton, Woodside, CA (US);
Brett W. Coon, San Jose, CA (US);
Kathleen Elliott Nickolls, Los Altos, CA (US);
Brian Fahs, Los Altos, CA (US);
John R. Nickolls, Los Altos, CA (US);
Henry Packard Moreton, Woodside, CA (US);
Brett W. Coon, San Jose, CA (US);
NVIDIA Corporation, Santa Clara, CA (US);
Abstract
One embodiment of the present invention sets forth a technique providing an optimized way to allocate and access memory across a plurality of thread/data lanes. Specifically, the device driver receives an instruction targeted to a memory set up as an array of structures of arrays. The device driver computes an address within the memory using information about the number of thread/data lanes and parameters from the instruction itself. The result is a memory allocation and access approach where the device driver properly computes the target address in the memory. Advantageously, processing efficiency is improved where memory in a parallel processing subsystem is internally stored and accessed as an array of structures of arrays, proportional to the SIMT/SIMD group width (the number of threads or lanes per execution group).