The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 10, 2014

Filed:

Feb. 02, 2012
Applicants:

Sorin S. Georgescu, San Jose, CA (US);

A. Peter Cosmin, Santa Clara, CA (US);

George Smarandoiu, San Jose, CA (US);

Inventors:

Sorin S. Georgescu, San Jose, CA (US);

A. Peter Cosmin, Santa Clara, CA (US);

George Smarandoiu, San Jose, CA (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); H01L 29/788 (2006.01); H01L 27/115 (2006.01);
U.S. Cl.
CPC ...
G11C 16/0458 (2013.01); H01L 27/11524 (2013.01);
Abstract

A non-volatile memory including one or more EEPROM cell pairs. Each EEPROM cell pair includes three transistors and stores two data bits, effectively providing a 1.5 transistor EEPROM cell. An EEPROM cell pair includes a first non-volatile memory transistor connected to a first bit line, a second non-volatile memory transistor connected to a second bit line, and a source access transistor coupled to common source line. The source access transistor includes: a first diffusion region continuous with a source region of the first non-volatile memory transistor and a second diffusion region continuous with a source region of the second non-volatile memory transistor.


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