The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 10, 2014

Filed:

Dec. 13, 2011
Applicants:

Bing-bing Xu, Jiangsu, CN;

Ju-ya Luo, Jiangsu, CN;

Zhao-long Dong, Jiangsu, CN;

Ching-ji Liang, Taipei, TW;

Inventors:

Bing-Bing Xu, Jiangsu, CN;

Ju-Ya Luo, Jiangsu, CN;

Zhao-Long Dong, Jiangsu, CN;

Ching-Ji Liang, Taipei, TW;

Assignee:

Asus Technology Pte Ltd, Eightrium, SG;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G05F 1/56 (2006.01);
U.S. Cl.
CPC ...
Abstract

A power circuit includes a control unit, a logic control circuit, a first driver amplifier, a second driver amplifier and a logic determination circuit. The control unit is used to output a pulse width modulation (PWM) signal and an enable (EN) signal. The logic control circuit receives the PWM signal and the EN signal, and outputs a first voltage signal and a second voltage signal. The first driver amplifier receives the first voltage signal, and outputs a first gate (UGATE) drive signal. The second driver amplifier receives the second voltage signal, and outputs a second gate (LGATE) drive signal. The logic determination circuit receives the PWM signal and the first and second gate drive signals. When the PWM signal and the first and second gate drive signals meet an abnormal logical relation, the logic determination circuit disables the logic control circuit.


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