The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 10, 2014

Filed:

Oct. 13, 2011
Applicants:

Sung Jin Whang, Seoul, KR;

Kwon Hong, Gyeonggi-do, KR;

Ki Hong Lee, Gyeonggi-do, KR;

Inventors:

Sung Jin Whang, Seoul, KR;

Kwon Hong, Gyeonggi-do, KR;

Ki Hong Lee, Gyeonggi-do, KR;

Assignee:

Hynix Semiconductor Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/788 (2006.01); H01L 27/115 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11556 (2013.01); H01L 29/7889 (2013.01);
Abstract

A three dimensional non-volatile memory structure includes a plurality of interlayer dielectric layers and a plurality of control gates alternately stacked over a substrate, a channel formed to penetrate the plurality of interlayer dielectric layers and the plurality of control gates, a tunnel insulating layer formed to surround the channel, a plurality of floating gates disposed between the plurality of interlayer dielectric layers and the tunnel insulating layer, wherein the plurality of floating gates each have a thickness greater than a corresponding one of the interlayer dielectric layers, and a charge blocking layer disposed between the plurality of control gates and the plurality of floating gates.


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