The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 10, 2014

Filed:

Sep. 27, 2012
Applicant:

Fairchild Semiconductor Corporation, San Jose, CA (US);

Inventor:

Krister Gumaelius, Vaxholm, SE;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor device and a method of forming a structure in a target substrate for manufacturing a semiconductor device is provided. The method comprises the step of providing a masking layer on the target substrate and providing a stair-like profile in the masking layer such that the height of a step of the stair-like profile is smaller than the thickness of the masking layer. Further, the method comprises the step of performing anisotropic etching of the masking layer and the target substrate simultaneously such that a structure having a stair-like profile is formed in the target substrate. The semiconductor device comprises a target substrate including a first region made of a first type of semiconductor material and a second region made of a second type of semiconductor material.


Find Patent Forward Citations

Gumaelius, Krister. (2014). Bipolar junction transistor with stair profile (U.S. Patent No. 8748943). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8748943

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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