The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 10, 2014

Filed:

Jun. 12, 2012
Applicants:

Kwang-wook Lee, Seongnam-Si, KR;

Sang-jun Lee, Seoul, KR;

In-seak Hwang, Suwon-si, KR;

In-sang Jeon, Seoul, KR;

Byoung-yong Gwak, Suwon-si, KR;

Ho-kyun an, Seoul, KR;

Inventors:

Kwang-wook Lee, Seongnam-Si, KR;

Sang-jun Lee, Seoul, KR;

In-seak Hwang, Suwon-si, KR;

In-sang Jeon, Seoul, KR;

Byoung-yong Gwak, Suwon-si, KR;

Ho-kyun An, Seoul, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of manufacturing a semiconductor device includes forming a bit line on a substrate comprising an active region; forming an interlayer insulating layer covering the bit line on the substrate; forming a first hole at a location of the active region through the interlayer insulating layer; forming a dummy contact layer by filling the first hole; forming a mold layer on the interlayer insulating layer and the dummy contact layer; forming a second hole at a location of the dummy contact layer through the mold layer; removing the dummy contact layer in the first hole through the second hole; forming an epitaxial layer on a portion of the active region, which is exposed at a lower surface of the first hole; and forming a lower electrode on internal surfaces of the first hole and the second hole.


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