The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 10, 2014

Filed:

Sep. 14, 2012
Applicants:

Mike Kwon, Pleasanton, CA (US);

Gerry Keller, Livermore, CA (US);

Scott West, Pleasanton, CA (US);

Tao Tong, Pleasanton, CA (US);

Babak Imangholi, Livermore, CA (US);

Inventors:

Mike Kwon, Pleasanton, CA (US);

Gerry Keller, Livermore, CA (US);

Scott West, Pleasanton, CA (US);

Tao Tong, Pleasanton, CA (US);

Babak Imangholi, Livermore, CA (US);

Assignee:

Bridgelux, Inc., Livermore, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of fabricating a substrate free light emitting diode (LED), includes arranging LED dies on a tape to form an LED wafer assembly, molding an encapsulation structure over at least one of the LED dies on a first side of the LED wafer assembly, removing the tape, forming a dielectric layer on a second side of the LED wafer assembly, forming an oversized contact region on the dielectric layer to form a virtual LED wafer assembly, and singulating the virtual LED wafer assembly into predetermined regions including at least one LED. The tape can be a carrier tape or a saw tape. Several LED dies can also be electrically coupled before the virtual LED wafer assembly is singulated into predetermined regions including at the electrically coupled LED dies.


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