The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 03, 2014

Filed:

Nov. 15, 2011
Applicants:

Damian P Yurzola, Santa Clara, CA (US);

Rajeev Nagabhirava, Santa Clara, CA (US);

Gary J Lin, San Jose, CA (US);

Matthew Davidson, Mountain View, CA (US);

Paul a Lassa, Cupertino, CA (US);

Inventors:

Damian P Yurzola, Santa Clara, CA (US);

Rajeev Nagabhirava, Santa Clara, CA (US);

Gary J Lin, San Jose, CA (US);

Matthew Davidson, Mountain View, CA (US);

Paul A Lassa, Cupertino, CA (US);

Assignee:

SanDisk Technologies, Inc., Milpitas, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/00 (2006.01); G06F 3/06 (2006.01); G06F 1/32 (2006.01); G06F 9/52 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0659 (2013.01); G06F 1/3203 (2013.01); G06F 9/52 (2013.01);
Abstract

Disclosed are apparatus and techniques for managing power in a memory system having a controller and nonvolatile memory array. In one embodiment, prior to execution of each command with respect to the memory array, a request for execution of such command is received with respect to the memory array. In response to receipt of each request for each command, execution of such command is allowed or withheld with respect to the memory array based on whether such command, together with execution of other commands, is estimated to exceed a predetermined power usage specification for the memory system.


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