The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 03, 2014

Filed:

Oct. 15, 2009
Applicants:

Peter Nilsson, Solna, SE;

Jürgen Leib, Singapore, SG;

Robert Thorslund, Solna, SE;

Inventors:

Peter Nilsson, Solna, SE;

Jürgen Leib, Singapore, SG;

Robert Thorslund, Solna, SE;

Assignee:

ÅAC Microtec AB, Uppsala, SE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/40 (2006.01); H01L 21/4763 (2006.01); H01L 21/44 (2006.01); H01L 25/16 (2006.01); H01L 23/48 (2006.01); H01L 25/065 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
B81C 1/0087 (2013.01); H01L 25/16 (2013.01); B81B 2207/096 (2013.01); H01L 23/481 (2013.01); H01L 25/0657 (2013.01); B81B 2207/07 (2013.01); B81B 2203/0353 (2013.01); H01L 2924/14 (2013.01); H01L 2224/0557 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06541 (2013.01); H01L 21/76898 (2013.01);
Abstract

The present invention provides a method of forming a via hole (), or a via (), from a lower side () of a substrate () for electronic devices towards an upper side () of a substrate () at least partly through the substrate (). The method comprises the steps of: etching a first lengthwise portion () of the via hole () and etching a second lengthwise portion () of the via hole (); whereby the first lengthwise portion () and the second lengthwise portion () substantially form the via hole () and a constriction () is formed in the via hole (). The constriction () defines an aperture () of the via hole () and the method further comprises the step of opening the via hole () by etching, with the constriction () functioning as an etch mask. A via is formed by at least partly filling the via hole with conductive material. A substrate for electronic devices comprising a via is also provided.


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