The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 03, 2014
Filed:
Dec. 02, 2009
Ku-hyun Kang, Yongin, KR;
Dong-jin Kim, Yongin, KR;
Yeon-il Kang, Yongin, KR;
Czang-ho Lee, Yongin, KR;
Myung-hun Shin, Yongin, KR;
Dae-ha Woo, Yongin, KR;
Byoung-kyu Lee, Yongin, KR;
Yuk-hyun Nam, Yongin, KR;
Seung-jae Jung, Yongin, KR;
Joong-hyun Park, Yongin, KR;
Ku-Hyun Kang, Yongin, KR;
Dong-Jin Kim, Yongin, KR;
Yeon-Il Kang, Yongin, KR;
Czang-Ho Lee, Yongin, KR;
Myung-Hun Shin, Yongin, KR;
Dae-Ha Woo, Yongin, KR;
Byoung-Kyu Lee, Yongin, KR;
Yuk-Hyun Nam, Yongin, KR;
Seung-Jae Jung, Yongin, KR;
Joong-Hyun Park, Yongin, KR;
Samsung SDI Co., Ltd., Yongin-Si, Gyeonggi-Do, KR;
Abstract
A solar cell module includes a substrate, a lower electrode layer, a semiconductor layer and an upper electrode layer for an embodiment. The lower electrode layer may include a plurality of area-separating grooves separating the substrate into an active area and a peripheral area surrounding the active area, and a plurality of first cell-separating grooves formed in the active area. The semiconductor layer is formed on the lower electrode layer. The semiconductor layer includes a plurality of second cell-separating grooves that are spaced apart from the first cell-separating grooves. The upper electrode layer is formed on the semiconductor layer. The upper electrode layer includes a plurality of third cell-separating grooves that are spaced apart from the second separating grooves.