The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 03, 2014
Filed:
Sep. 20, 2007
Dan O. Popa, Arlington, TX (US);
Rachita Dewan, Washington, DC (US);
Praveen Pandojirao-sunkojirao, Arlington, TX (US);
Jung-chih Chiao, Grand Prairie, TX (US);
Dan O. Popa, Arlington, TX (US);
Rachita Dewan, Washington, DC (US);
Praveen Pandojirao-Sunkojirao, Arlington, TX (US);
Jung-Chih Chiao, Grand Prairie, TX (US);
Board of Regents, The University of Texas System, Austin, TX (US);
Abstract
Described are three-dimensional stacked semiconductor structures having one or more vertical interconnects. Vertical stacking relies on vertical interconnects and wafer bonding using a patternable polymer. The polymer is preferably lithographically patternable and photosensitive. Curing of the polymer is preselected from about 35% to up to about 100%, depending on a desired outcome. When fabricated, such vertically stacked structures include electrical interconnects provided by solder reflow. Solder reflow temperature is bounded by a curing and glass transition temperatures of a polymer used for bonding.