The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 27, 2014
Filed:
Apr. 21, 2010
Valeria Bertacco, Ann Arbor, MI (US);
Debapriya Chatterjee, Ann Arbor, MI (US);
Andrew Deorio, Ann Arbor, MI (US);
Valeria Bertacco, Ann Arbor, MI (US);
Debapriya Chatterjee, Ann Arbor, MI (US);
Andrew Deorio, Ann Arbor, MI (US);
The Regents of the University of Michigan, Ann Arbor, MI (US);
Abstract
Techniques for simulating operation of a connectivity level description of an integrated circuit design are provided, for example, to simulate logic elements expressed through a netlist description. The techniques utilize a host processor selectively partitioning and optimizing the descriptions of the integrated circuit design for efficient simulation on a parallel processor, more particularly a SIMD processor. The description may be segmented into cluster groups, for example macro-gates, formed of logic elements, where the cluster groups are sized for parallel simulation on the parallel processor. Simulation may occur in an oblivious as well as event-driven manner, depending on the implementation.