The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 27, 2014

Filed:

Nov. 22, 2011
Applicants:

Yoshiro Riho, Tokyo, JP;

Hiromasa Noda, Tokyo, JP;

Kazuki Sakuma, Tokyo, JP;

Inventors:

Yoshiro Riho, Tokyo, JP;

Hiromasa Noda, Tokyo, JP;

Kazuki Sakuma, Tokyo, JP;

Assignee:

Other;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 29/50 (2006.01); G11C 29/02 (2006.01); G11C 29/06 (2006.01); G11C 29/12 (2006.01); G11C 29/28 (2006.01);
U.S. Cl.
CPC ...
G11C 29/50 (2013.01); G11C 29/02 (2013.01); G11C 29/06 (2013.01); G11C 29/12005 (2013.01); G11C 29/28 (2013.01); G11C 2029/1202 (2013.01);
Abstract

A semiconductor device includes a memory cell array that is divided into a plurality of memory cell mats by a plurality of sense amplifier arrays. Each of the plurality of memory cell mats includes a plurality of word lines and a test circuit for performing a test control to activate, at one time, a plurality of word lines included in each of a plurality of selected memory cell mats that are not disposed adjacent each other in the plurality of memory cell mats. The memory cell mats with the plurality of activated word lines are distributed. Therefore, the load applied to a driver circuit for driving word lines and the load applied to a power supply circuit for supplying an operation voltage to the driver circuit are reduced.


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